{"step": "verc (voltage domains, power, thermal)", "ok": true, "status": "VERC_OK (0 warning(s))"}
{"step": "netaudit (graph = schematic = pcb)", "ok": true, "status": "NETAUDIT_OK (0 warning(s))"}
{"step": "KiCad DRC", "ok": true, "status": "DRC_OK"}
{"step": "power loops + decoupling", "ok": true, "status": "LOOPS_OK: 0 error(s), 1 warning(s)"}
{"step": "placement rules", "ok": true, "status": "PLACE_OK: 2 of 6 placement rules outside limits, 0 review finding(s) (warnings); anchors: run/out/place_anchors.png"}
{"step": "JLC CPL emulation", "ok": true, "status": "CPL_OK"}
{"step": "JLC stock (3 boards)", "ok": true, "status": "STOCK_OK"}
{"step": "render", "ok": true, "status": ""}