{"step": "verc (voltage domains, power, thermal)", "ok": true, "status": "VERC_OK (0 warning(s))"}
{"step": "netaudit (graph = schematic = pcb)", "ok": true, "status": "NETAUDIT_OK (0 warning(s))"}
{"step": "KiCad DRC", "ok": true, "status": "DRC_OK"}
{"step": "power loops + decoupling", "ok": true, "status": "LOOPS_OK: 0 error(s), 3 warning(s)"}
{"step": "placement rules", "ok": true, "status": "PLACE_OK: 7 of 27 placement rules outside limits, 10 review finding(s) (warnings); anchors: run/out/place_anchors.png"}
{"step": "JLC CPL emulation", "ok": true, "status": "CPL_OK (5 land-pattern warnings: E1,U5,U7,U9,U10)"}
{"step": "JLC stock (3 boards)", "ok": true, "status": "STOCK_OK"}
{"step": "3D models (warning only)", "ok": true, "status": "MODELS3D_OK: all 74 parts with a body have a 3D model (4 without one by design: H, H, H, H)"}
{"step": "render", "ok": true, "status": ""}