Example · designed with faezor
USB-C to UART Adapter (CH340C, 3.3 V)
Small USB-C to 3.3 V serial (UART) adapter based on the WCH CH340C, with TX/RX/power LEDs, ESD protection and an 8-pin 2.54 mm header (GND, 5V, 3V3, TXD, RXD, DTR, RTS, CTS).
Inspect in KiCad
The board in KiCad's own PCB editor, in your browser - read-only: zoom, look at every layer and
part, nothing can be changed. It needs desktop Chrome or Edge.
KiCad® (GPL-3.0 ) · source · build
KiCad® is a registered trademark of LF Projects, LLC. faezor is not affiliated with or endorsed by the KiCad project.
Render, top Render, bottom Board view Power loops & decoupling Assembly emulation Assembly emulation, top Live preview (copper)
All checks passed 8 verification steps
OK
verc (voltage domains, power, thermal)VERC_OK (0 warning(s))
OK
netaudit (graph = schematic = pcb)NETAUDIT_OK (0 warning(s))
OK
KiCad DRCDRC_OK
OK
power loops + decouplingLOOPS_OK: 0 error(s), 1 warning(s)
OK
placement rulesPLACE_OK: 2 of 6 placement rules outside limits, 0 review finding(s) (warnings); anchors: run/out/place_anchors.png
OK
JLC CPL emulationCPL_OK
OK
JLC stock (3 boards)STOCK_OK
OK
render
3D model (glTF) board.glb · 134.8 KB Render, top render_top.png · 104.5 KB Render, bottom render_bottom.png · 81.2 KB Schematic (PDF) schematic.pdf · 95.9 KB Gerbers + drill for JLCPCB gerbers_jlcpcb.zip · 50.8 KB BOM for JLCPCB assembly bom_jlc.csv · 642 B Full BOM bom_full.csv · 906 B Pick & place (CPL) cpl_jlc.csv · 770 B Verification summary check_summary.jsonl · 692 B Electrical review (voltage domains, power, thermal) verc_report.md · 5.4 KB JLC stock check stock_check.txt · 1.3 KB Placement review place_rules.md · 676 B
Download all outputs (.zip)
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